Drain-extended MOS (DEMOS) devices are used extensively in analog circuits as interfaces between low-voltage processing circuitry and high-voltage devices that are located off a chip in which the DEMOS devices are located. The use of DEMOS devices as interface elements often places them in the critical path of electrostatic discharge (ESD). DEMOS devices are well known for having poor drain-to-source ESD current handling capability due to kirk-effect induced voltage snapback. Isolated DEMOS devices are also vulnerable to failures induced by their parasitic transistors coupling them to isolation.
The current ESD protection techniques for DEMOS devices involves either using parallel ESD clamps or relying on self protection. Insertion of parallel ESD clamps typically requires significant area on the chip and may impose limitations on the maximum slew-rate of the output signal during operation. Self protection is not always practical because the gate voltages of the output transistors intrinsic in a DEMOS device cannot be guaranteed to stay on during ESD events. For example, the parasitic paths and circuit loading cause situations where robust self protection can be achieved only by relying on the current handling capability of the transistor in breakdown mode. Self protection in breakdown mode however requires the protected devices being large enough to enable self-protection. For example, self protection of a 2 kV discharge typically requires a total device width greater than 10,000 um and requires the breakdown current (IT1) to scale with the device width and number of gate fingers.